The present invention relates to synchronously operated memories and, more particularly, to multiple latency synchronous operation of dynamic random access memories.
Conventional non-pipelined dynamic random access memories (DRAMs) perform data transfers in sequence. That is, when a read or write command is received and an address is made available, the data transfer, either read or write, is performed in its entirety before another command is accepted. Consequently, subsequent commands are delayed by the entire duration of the original data transfer. Because data transfers typically involve several steps and each step takes time, the overall time to perform the original data transfer may be significant. For example, for a read, the control logic of the DRAM must decode the command and the address, provide signals, such as the row address select signal {overscore (RAS)}, and column address select signal {overscore (CAS)}, perform precharge and equalization, address the memory array, allow time for sense amplifiers to develop signals, and transfer data from the sense amplifiers to output registers. Subsequent commands must wait until these operations are completed before they are accepted by the DRAM. Consequently, either the clock speed of the DRAM must be sufficiently slow to allow the original data transfer to be completed before a subsequent command is provided, or a dummy command, such as no-operation command NO-OP, must be provided at all clock edges until the data transfer is complete.
To reduce the amount of delay imposed in sequential data transfer operations, DRAMs can be xe2x80x9cpipelined.xe2x80x9d In pipelining, each of the above-described steps is performed according to a specific timing sequence. For example, when the original data transfer progresses from a first step (e.g., command decode and address decode) to a second step (e.g., read data), a second data transfer progresses to the first step (command and address decode). Thus, the control logic can been decoding the second command and an address decoder can begin decoding the second address while the data from the original data transfer is being read from or written to the memory array.
To control the flow of data through a pipelined DRAM, commands and data are transferred synchronously. In synchronous operation, the timing sequence is established relative to leading edges of a clock signal. At fixed times relative to the leading edges, commands are read by the control logic, addresses are provided at an address input, signals are developed on input and output lines of the memory array, and data is made available for reading or writing at a data bus.
In synchronous read operations, an output of data on the data bus results from a command and an address received at a preceding leading edge of the clock. The delay in number of clock cycles between the arrival of the read command at the input to the control logic and the availability of data at the data bus is the xe2x80x9clatencyxe2x80x9d of the pipelined DRAM. If the output data is available by the second leading edge of the clock following the arrival of the read command, the device is described as a two latency DRAM. If the data is available at the third leading edge of the clock following the arrival of the read command, the device is a three latency DRAM.
In conventional pipelined DRAMs, latency is only imposed for read operations. In write and block write operations, write and block write commands are supplied simultaneously with data at the data bus and transferred to the memory array as quickly as possible. Typical pipelined DRAMs may thus be described as having no write latency. Nevertheless, write and block write operations may take more than one clock period. In such cases, data from the write or block write may require the data bus for more than one leading edge of the clock. Consequently, a no operation command NO-OP may be required to prevent data collision after a write or block write commands.
Conventionally, control logic and data paths within two latency and three latency DRAMs are optimized for the particular latency of the device. By accurately controlling the timing of each step of the data transfer operation, decoded addresses, data and enabling signals arrive at the memory array substantially simultaneously. In response, signal development at the sense amplifiers begins at a prescribed time. Because the time at which data is to be output is determined by the latency (2 or 3 clock periods), the timing of signal development at the sense amplifiers can be optimized. Conversely, if the time necessary for signal development is known, the clock speed can be optimized for the amount of time necessary to perform all of the steps of the data transfer. In such pipelined DRAMs, the time period in which the data bus and address bus are occupied can be controlled accurately and the time at which the data bus and address bus are available for subsequent addresses and data is known. By tightly controlling the timing of signals on the address, command and data buses, the speed of data transfer through the DRAM can be optimized and data and command collisions can be minimized.
The timing requirements for two latency and three latency operation may differ. Therefore, devices are typically optimized for either two latency or three latency operation. Because three latency operation allows an additional clock cycle between the acceptance of a command and the actual transfer of data from the memory array, the clock speed of three latency devices is typically higher than for two latency devices.
An integrated multiple latency synchronous dynamic random access memory includes as its central element a memory array. The multiple latency synchronous dynamic random access memory receives externally produced command signals, data, and row and column addresses. In response, the multiple latency synchronous dynamic random access memory performs data transfer operations, including reading from the memory array and writing or block writing, to the memory array.
The multiple latency synchronous dynamic random access memory receives the row and column addresses at an address register. Row addresses are transmitted to the memory array along a row address path. Column address follow a column address path to an IO interface coupled to the memory array. A logic controller receives and decodes the command signals to identify commands. The logic controller also receives data indicating whether two latency or three latency operation is selected. Based upon the decoded commands and the selected two or three latency operation, the logic controller controls the timing of the operations in the multiple latency synchronous dynamic random access memory by controlling the IO interface. Through its control of the IO interface, the logic controller also controls the transfer of addresses and data to and from the memory array.
The selection between two and three latency operation is made by a user. To select two latency mode, the user provides a xe2x80x9c010xe2x80x9d sequence of address bits and a defined set of command signals. To select three latency mode, a user supplies a xe2x80x9c110xe2x80x9d sequence of address bits and the defined set of command signals. In response to the defined set of command signals and the sequence address bits, a latency select circuit selects either two or three latency operation and produces a two latency signal or a three latency signal in response.
Control of the timing for two and three latency operation in the multiple latency synchronous dynamic random access memory is established within a latency control circuit in the logic controller. The latency control circuit includes an input latch section, a two latency control section and a three latency control section. The input latch section receives the command signals and produces a read signal, write signal and block write signal for input to the two and three latency control sections.
The two latency control section receives the read, write and block write signals from the input latch section. The two latency control section also receives the clock signal and the two latency signal produced by the latency select circuit. In response to these signals, the two latency control section produces several control signals, including a precharge signal, a decode enable signal and enable write signal, and a master-slave write pass signal. Each of the control signals is produced according to a two latency timing algorithm in the two latency control section.
The three latency control section also receives the read, write and block write signals, the clock signal, and the three latency signal produced by the latency select circuit. The three latency control section produces the same control signals as the two latency control section and also produces a master-slave write pass signal. However, the timing algorithm according to which the three latency control section produces the control signals is different from the timing algorithm of the two latency control section. Consequently, separate and independent circuits control the timing of control signals for two or three latency operation.
A reset signal within the three latency control section is fed back to the input latch section to control the timing of the read, write and block write signals from the input latch section. In two latency operation, the read, write and block write signals are produced quickly by the input latch section. In three latency operation, the read, write and block write signals are delayed until the reset signal arrives. Consequently, in three latency operation, the read, write and block write signals are pipelined.
For writing to the memory array, data arrives at a data bus and follows a data path from the data bus to the IO controller. Within the data path, data is clocked into a master input register under control of the logic controller 102. Data from the master input register is then clocked from the master input register into a pair of slave registers and a color register. In two latency operation, the data is closed immediate from the master input register to the slave registers and color register. In three latency operation, clocking of data is delayed by approximately one clock period.
For read operations, data follows one of two output data paths. In three latency operation, the data is clocked into a master output register. Subsequently, data is clocked from the master output register to an output section by a gate controlled by the logic controller. Because the logic controller imposes a delay of approximately 1 clock cycle on the gating of data from the master output register to the data bus, the multiple latency synchronous dynamic random access memory can be said to have a write latency in three latency operation.
In two latency operation, data from the IO interface bypasses the master output register through a bypass path. The bypass path provides a direct path for data without the delay imposed by the master output register. Consequently, in two latency operation, data passes quickly from the IO interface to the data bus.